This book is based on the design of DRAM (GC-eDRAM) embedded in a gain cell for low-power VLSI systems (SoCs). Novel GC-eDRAMs is specifically designed for a range of low-power VLSI products, ranging from ultra-low power to high-performance, efficient applications.

After a detailed review of the previous GC-eDRAM system, an analytical holding time distribution model was presented and validated by silicon measurements, which is the key to low-energy GC-eDRAM design. The book then checks the voltage and near voltage (NTV) of the conventional gain cell (GC) before introducing the new GC technology and helping the NTV operation techniques, including the transistor transistor output in three transistors, the RBB, Symmetry to determine optimal update time.

Next, the traditional GC bitccs are evaluated under aggressive technique and voltage measurement (down to the subdomain), before using the new Bitcells to hold the high-resolution CMOS and tolerate the soft errors as they were introduced, including GC-4 transistor with partial internal observations and 4 GC transistor with built-in redundancy.